The present invention relates to a product adder of a computer and, more particularly, to a product adder for performing multiplication of floating-point data and addition of fixed-point data.
FIG. 5 shows an arrangement of blocks of a conventional product adder, and FIG. 6 shows an arrangement of blocks of another conventional product adder.
Conventionally, a product adder for processing fixed-point data in both multiplication and addition has an arrangement as shown in FIG. 5. An example of execution of EQU AX1+BX2 (A=0.1100000B, X1=0.1110000B, B=0.1010000B, and X2=0.1010000B where B represents binary notation)
will be described below with reference to FIG. 5.
When addresses of data as inputs to a multiplier are set in pointers 19 and 20, two 8-bit fixed-point data EQU A=0.1100000, X1=0.1110000
are read out from memories 17 and 18, respectively. A multiplier 16 performs multiplication of the readout fixed-point data and outputs 16-bit fixed-point data EQU AX1=0.101010000000000B.
Eight upper bits 01010100 of the output data are stored in a register 21, and its eight lower bits 00000000 are stored in a register 22. The contents of the register 22, i.e., the eight lower bits 00000000 are selected by a multiplexer 23 and added to a value (initially, 00000000) stored in an accumulator 25 by a full adder 24. The sum is stored in the accumulator 25.
Subsequently, the contents of the register 21, i.e., the eight upper bits 01010100 are selected by the multiplexer 23 and added to a value (initially, 00000000) stored in an accumulator 26 by the full adder 24. The sum is stored in the accumulator 26. When addresses of data for performing multiplication are set in the pointers 19 and 20, two 8-bit fixed-point data EQU B=0.1010000B, X2=0.1010000B
are read out from the memories 17 and 18, respectively, and the multiplier 16 performs multiplication of the readout fixed-point data and outputs 16-bit fixed-point data EQU BX2=0.011001000000000B.
Eight upper bits 00110010 of the output data are stored in the register 21, and its eight lower bits 00000000 are stored in the register 22.
The contents of the register 22, i.e., the eight lower bits 00000000 are selected by the multiplexer 23 and added to 00000000 stored in the accumulator 25 by the full adder 24, i.e., addition 0000000+00000000 is executed by the full adder 24. The sum 00000000 is stored in the accumulator 25. The contents of the register 21, i.e., the eight upper bits 00110010 are selected by the multiplexer 23 and similarly added to 01010100 stored in the accumulator 26 by the full adder 24, i.e., addition 00110010+01010100 is executed by the full adder 24. The sum causes an overflow. Therefore, as overflow processing, a positive maximum value 01111111 is taken as the sum and stored in the accumulator 26. A sum of the values of the accumulators 25 and 26, i.e., 0.111111100000000B is stored as a product sum in the memory 18.
An example of execution of product addition
AX1+BX2 (A=0.11000.times.2.sup.00, X1=0.11100.times.2.sup.00, B=0.10100.times.2.sup.00, and X2=0.10100.times.2.sup.00)
performed in a conventional product adder for processing floating-point data in both multiplication and addition will be described below with reference to FIG. 6.
When addresses of input data to a multiplexer 1 are set in pointers 4 and 5, two 8-bit floating-point data EQU A=0.11000.times.2.sup.00, X1=0.11100.times.2.sup.00
each having a two-bit exponential part and a six-bit mantissa part are read out from memories 2 and 3, and a multiplier 1 performs multiplication of the readout floating-point data. The product EQU AX1=0.10101000000.times.2.sup.00 (exponential part=two bits, mantissa part=12 bits)
is stored in a register 27. The product AX1 is stored in an accumulator 33 via a switch 30, a barrel shifter 31, and a full adder 32.
When addresses of input data to the multiplier 1 are set in the pointers 4 and 5, two 8-bit floating-point data EQU B=0.10100.times.2.sup.00, X2=0.10100.times.2.sup.00
each having a two-bit exponential part and a six-bit mantissa part are read out from the memories 2 and 3, respectively, and the multiplier 1 performs multiplication of the readout floating-point data. The product EQU BX2=0.01100100000.times.2.sup.00 (exponential part=two bits, mantissa part=12 bits)
is stored in the register 27. The value EQU AX1=0.10101000000.times.2.sup.00 (exponential part=two bits, mantissa part=four bits)
of the accumulator 33 is stored in the register 28.
Subsequently, an EAU (Exponent Arithmetic Unit) 29 compares the exponential parts 00B of the data BX2 and AX1 stored in the registers 27 and 28, and the barrel shifter 31 shifts the digits of the mantissa parts of the data AX1 and BX2 so that a smaller exponential part becomes equal to a larger exponential part. In this embodiment, no shifting is performed by the barrel shifter 31 because the two exponential parts are the same.
The full adder 32 performs addition of the mantissa parts of the data AX1 and BX2. That is, 0.10101000000B+0.01100100000B is executed. This sum of the mantissa parts is 1.0001100000B, i.e., causes an overflow. Therefore, the following compensation of floating-point addition is performed. That is, the mantissa part is shifted to the right by one bit by the shifter 34, and "1" is added to the output 00B from the EAU 29 as the exponential part to obtain 01B. The mantissa part 0.10000110000B is stored in 12 lower bits of the accumulator 33, and the exponential part 01B is stored in its two upper bits. The value of the accumulator 33, i.e., 0.10000110000.times.2.sup.01 is stored as a product sum in the memory 3.
However, in the above conventional product adder for processing fixed-point data in both multiplication and addition, the number of bits as an output result of the 6-bit x 6-bit multiplier is 12. Therefore, addition is performed twice for the upper and lower bits in the 12-bit full adder, resulting in a low operation speed. In addition, since the number of bits of a product sum is doubled, the size of a memory for storing the sum is increased. Furthermore, the dynamic range of data to be processed is limited to degrade accuracy.
In the above conventional product adder for processing floating-point data in both multiplication and addition, the circuit size is increased, and the size of a memory for storing data is increased.